1. Field of the Invention
This invention relates to a seimconductor device of an integrated circuit (IC) and more particularly to an IC device which includes a plurality of field effect transistors (FETs), at least one of which has a back-gate electrode.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a circuit diagram including a conventional dynamic memory cell and a decoder for selecting a memory cell. This dynamic memory cell comprises a capacitor 1 for storing charge corresponding to a binary memory information of "1" or "0" and an N channel FET 5 for bidirectionally controlling read and write of data. An electrode 2 of the capacitor 1 is connected through a node 10 to a source (or drain) electrode 7 of the FET 5, while the other electrode 3 is connected to a terminal 4 which is supplied with a given voltage. A drain (or source) electrode 6 of the FET 5 is connected through a node 14 to a bit line 11 for transmitting data. A gate electrode 8 of the FET 5 is connected through a node 13 to a word line 12 which is supplied with a signal for selecting a memory cell. A back-gate electrode 9 of the FET 5 is connected to a terminal 15 which is supplied with a given voltage.
A decoder 16 has input terminals 17 and an output terminal 18. The input terminals 17 receive address signals (A.sub.1, A.sub.1, . . . , A.sub.n, A.sub.n) for selecting a word line 12. An N channel FET 19 transmits a clock signal .phi. on a signal input terminal 24a to the word line 12, depending on the potential level at the output terminal 18. The FET 19 has a drain (or source) electrode 20 connected to the signal input terminal 24a, a source (or drain) electrode 21 connected to the word line 12, a gate electrode 22 connected to the output terminal 18 and a back-gate electrode 23 connected to a voltage terminal 15.
In operation of reading data from the memory cell, when the decoder 16 is selected by the address signals (A.sub.1, A.sub.1, . . . A.sub.n, A.sub.n), the level of the output terminal 18 become "H" ("1") and then the FET 19 is turned on. When the clock signal .phi. changes from "L" level to "H" level, the level of the word line 12 changes from "L" to "H" with the FET 19 being turned on. At this time, since the FET 5 is turned on, the electrode 2 is connected with the bit line 11 and then data is read out from the memory cell. In order to make this read operation faster, it is desired that both the FETs 5 and 19 can be readily turned on. To achieve this, the threshold voltages V.sub.TH5 and V.sub.TH19 of the respective FETs 5 and 9 may be set as low as possible.
On the other hand, the memory cell has to hold data even when the level of the bit line 11 is "L". When the level of the word line 12 becomes "L", the FET 5 is turned off. If "L" level is read from another cell (not shown) through the same bit line 11, the level of the bit line 11 becomes "L", i.e., "0". In the case that the threshold voltage V.sub.TH5 of the FET 5 is set lower to make read operation faster, a small leak current will flow from the source electrode 7 of the FET 5 to the drain electrode 6, even though the voltage of the gate electrode 8 is lower than the threshold voltage V.sub.TH5. As a result, when the potential of the bit line 11 is O and "H" level is stored in the capacitor 1, the stored charge flows little by little from the electrode 2 to bit line 11 through the FET 5 and finally the capacitor 1 becomes "L" level. Namely, data in the memory cell disappears. This means erroneous operation of the memory circuit.
In order to prevent such erroneous operation, the threshold voltage V.sub.TH5 of the FET 5 is generally set to be higher than the threshold voltage V.sub.TH19 of the FET 19. To this end, the channel region of the N channel FET 5 is selectively doped with P type dopant by ion implantation or the like. This additional step in the manufacturing process involves increase of the cost.
Incidentally, some IC devices which include FETs having back-gate electrodes are described in the Japanese Patent Laying-Open Gazette No. 72691/1979.